1. Field of the Invention
The present invention relates in general to a printed circuit board (PCB), and more particularly, to a printed circuit board which is improved in the structure of lands to be connected to solder balls of a semiconductor chip package.
2. Description of the Related Art
Generally, a semiconductor chip package is classified into a dual in-line package (DIP or IMT) type package and a surface mount technology (SMT) type package. Recently, compared with the IMT package, the SMT package has been widely used to enhance the mounting efficiency of the package to a PCB in line with a miniaturization of electronic appliances. As examples of the SMT package, there is the QFP (quad flat package), the PLCC (plastic leaded chip carrier), the CLCC (ceramic leaded chip carrier), the BGA (ball grid array), etc.
As illustrated in FIG. 1, a BGA package 5, as an example of an SMT package is comprised of a substrate 7 made of a ceramic or epoxy, a circuit pattern 8 formed on the substrate 7, a solder mask 9 coated on the circuit pattern 8, a semiconductor chip 3 mounted on the center of the substrate 7, and a wire 4 electrically connecting the circuit pattern 8 with the semiconductor chip 3. The semiconductor chip 3 and the wire 4 are covered with a resin cover 6 to prevent oxidation and corrosion. On a lower surface of the substrate 7 facing a printed circuit board 1 is provided a plurality of solder balls 10 which are electrically connected to the substrate 7. The BGA package 5 is mounted on the printed circuit board 1 by the solder balls 10.
In the BGA package 5, a signal outputted from the semiconductor chip 3 is transmitted to the circuit pattern 8 through the wire 4. The signal from the circuit pattern 8 is transmitted to the printed circuit board 1 through the solder balls 10, and then the signal is transmitted to peripheral chips (not shown). On the other hand, in the case where signals are transmitted from the peripheral chips to the semiconductor chip 3, the signals are transmitted in the reverse order.
As shown in FIG. 3, the solder balls 10 are provided on the lower surface of the substrate 7 in areas other than the center area, at regular intervals, and each solder ball 10 has the same size with respect to each other.
On the printed circuit board 51 are provided a plurality of lands 65 at positions corresponding to the solder balls 10 to mount the BGA package 5. The lands 65 have uniform sizes corresponding to the size of the solder balls 10.
Further, on the printed circuit board 51 are provided traces 70, namely, wiring patterns in order to electrically connect the BGA package or CSP (Chip Scale Package) with the peripheral chips mounted on the printed circuit board 51. However, it is hard to connect the traces 70 with the lands 65 positioned at the inside area of the printed circuit board 51 because the widths between the lands 65 are so narrow that plural traces 70 cannot easily pass therethrough. Accordingly, in the case of a multi-layered printed circuit board 51, there has been proposed a method of making via-holes in the lands 65 of the printed circuit board 51, thereby connecting the traces 70 with the inside lands 65 through the via-holes.
However, because the printed circuit board 51 should have the via-holes, and then the wiring pattern of the layer formed with the via-holes should be connected to the wiring pattern of the layer mounted with the BGA package 5 or the CSP, the design of the printed circuit board 51 becomes complicated. Moreover, if the via-holes are not satisfactory for accommodating the traces 70, a space between the lands 65 can be secured by decreasing the size of each land 65, so as to accommodate the traces 70 in the spaces. However, in this case, there is a problem that a soldering state between the solder ball 10 and the land 65 is poor because the amount of the solder connecting the land 65 with the solder ball 10 is decreased.
Thus, in the case of the printed circuit board 51 mounted with a plurality of BGA packages or CSP, it is necessary to secure a predetermined space between the lands 65. However, this lowers the level of integration of the peripheral chips on the printed circuit board 51.